Project Statistics |
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PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_ProjectDescription=Example of prototyping the Timer_MMSS into a NEXYS 2 board from Digilent |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2017-12-08T16:43:30 |
PROP_intWbtProjectID=E39004A700694042BFAE36691096E094 |
PROP_intWbtProjectIteration=3 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s500e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=fg320 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-5 |
PROP_PreferredLanguage=VHDL |
FILE_UCF=1 |
FILE_VHDL=21 |