Timer_MMSS_NEXYS2 Project Status (05/16/2018 - 19:40:38) | |||
Project File: | Timer_MMSS_NEXYS2_prj.xise | Parser Errors: | No Errors |
Module Name: | Timer_MMSS_NEXYS2 | Implementation State: | Synthesized |
Target Device: | xc3s500e-5fg320 |
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No Errors |
Product Version: | ISE 14.7 |
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44 Warnings (42 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 91 | 4656 | 1% | |
Number of Slice Flip Flops | 53 | 9312 | 0% | |
Number of 4 input LUTs | 175 | 9312 | 1% | |
Number of bonded IOBs | 21 | 232 | 9% | |
Number of GCLKs | 1 | 24 | 4% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | mi. 16. may. 19:40:31 2018 | 0 | 44 Warnings (42 new) | 2 Infos (0 new) | |
Translation Report | Out of Date | vi. 8. dic. 17:14:32 2017 | 0 | 0 | 0 | |
Map Report | Out of Date | vi. 8. dic. 17:14:41 2017 | 0 | 2 Warnings (0 new) | 2 Infos (0 new) | |
Place and Route Report | Out of Date | vi. 8. dic. 17:15:23 2017 | 0 | 2 Warnings (1 new) | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Out of Date | vi. 8. dic. 17:15:28 2017 | ||||
Bitgen Report | Out of Date | vi. 8. dic. 17:17:27 2017 | 0 | 1 Warning (0 new) | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
Post-Synthesis Simulation Model Report | Out of Date | vi. 8. dic. 17:16:11 2017 | |
Post-Map Static Timing Report | Out of Date | vi. 8. dic. 17:16:40 2017 | |
Post-Map Simulation Model Report | Out of Date | vi. 8. dic. 17:16:50 2017 | |
WebTalk Report | Out of Date | vi. 8. dic. 17:17:28 2017 | |
WebTalk Log File | Out of Date | vi. 8. dic. 17:17:33 2017 |