Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s500e
Project ID (random number) 6b4c511123ad450fbddd12dd1e22375b.E39004A700694042BFAE36691096E094.3 Target Package: fg320
Registration ID 211002151_0_0_552 Target Speed: -5
Date Generated 2017-12-08T17:17:28 Tool Flow ISE
 
User Environment
OS Name Microsoft , 64-bit OS Release major release (build 9200)
CPU Name Intel(R) Xeon(R) CPU X5670 @ 2.93GHz CPU Speed 2934 MHz
CPU Name Intel(R) Xeon(R) CPU X5670 @ 2.93GHz CPU Speed 2934 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=4
  • 4-bit addsub=4
Comparators=12
  • 4-bit comparator greater=4
  • 4-bit comparator less=4
  • 5-bit comparator less=1
  • 7-bit comparator less=3
Counters=4
  • 5-bit up counter=1
  • 7-bit up counter=3
Decoders=1
  • 1-of-4 decoder=1
FSMs=2 Multiplexers=1
  • 4-bit 4-to-1 multiplexer=1
ROMs=1
  • 16x7-bit ROM=1
Registers=21
  • Flip-Flops=21
MiscellaneousStatistics
  • AGG_BONDED_IO=21
  • AGG_IO=21
  • AGG_SLICE=94
  • NUM_4_INPUT_LUT=176
  • NUM_BONDED_IBUF=6
  • NUM_BONDED_IOB=15
  • NUM_BUFGMUX=1
  • NUM_LUT_RT=1
  • NUM_SHIFT=1
  • NUM_SLICEL=93
  • NUM_SLICEM=1
  • NUM_SLICE_FF=53
NetStatistics
  • NumNets_Active=193
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=45
  • NumNodesOfType_Active_CNTRLPIN=60
  • NumNodesOfType_Active_DOUBLE=282
  • NumNodesOfType_Active_DUMMY=626
  • NumNodesOfType_Active_DUMMYESC=6
  • NumNodesOfType_Active_GLOBAL=11
  • NumNodesOfType_Active_HFULLHEX=2
  • NumNodesOfType_Active_HUNIHEX=11
  • NumNodesOfType_Active_INPUT=659
  • NumNodesOfType_Active_IOBOUTPUT=6
  • NumNodesOfType_Active_OMUX=223
  • NumNodesOfType_Active_OUTPUT=166
  • NumNodesOfType_Active_PREBXBY=150
  • NumNodesOfType_Active_VFULLHEX=12
  • NumNodesOfType_Active_VLONG=3
  • NumNodesOfType_Active_VUNIHEX=26
  • NumNodesOfType_Gnd_DUMMY=4
  • NumNodesOfType_Gnd_INPUT=4
  • NumNodesOfType_Gnd_OMUX=1
  • NumNodesOfType_Gnd_OUTPUT=1
  • NumNodesOfType_Gnd_PREBXBY=2
  • NumNodesOfType_Vcc_CNTRLPIN=2
  • NumNodesOfType_Vcc_VCCOUT=2
SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=8
  • IOB-DIFFS=6
  • SLICEL-SLICEM=48
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=6
  • IBUF_INBUF=6
  • IBUF_PAD=6
  • IOB=15
  • IOB_OUTBUF=15
  • IOB_PAD=15
  • SLICEL=93
  • SLICEL_F=85
  • SLICEL_F5MUX=14
  • SLICEL_FFX=36
  • SLICEL_FFY=16
  • SLICEL_G=90
  • SLICEM=1
  • SLICEM_FFY=1
  • SLICEM_G=1
  • SLICEM_WSGEN=1
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:6]
IOB
  • O1=[O1_INV:0] [O1:15]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:15]
IOB_PAD
  • DRIVEATTRBOX=[12:15]
  • IOATTRBOX=[LVCMOS25:15]
  • SLEW=[SLOW:15]
SLICEL
  • BX=[BX_INV:0] [BX:15]
  • BY=[BY:1] [BY_INV:1]
  • CE=[CE:17] [CE_INV:0]
  • CLK=[CLK:44] [CLK_INV:0]
  • SR=[SR:43] [SR_INV:0]
SLICEL_F5MUX
  • S0=[S0:14] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:13] [CE_INV:0]
  • CK=[CK:36] [CK_INV:0]
  • D=[D:36] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:36]
  • FFX_SR_ATTR=[SRLOW:36]
  • LATCH_OR_FF=[FF:36]
  • SR=[SR:35] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:36]
SLICEL_FFY
  • CE=[CE:7] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • D=[D:15] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:16]
  • FFY_SR_ATTR=[SRLOW:16]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:15] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:16]
SLICEM
  • BY=[BY:1] [BY_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:0]
SLICEM_FFY
  • CK=[CK:1] [CK_INV:0]
  • D=[D:1] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:1]
  • FFY_SR_ATTR=[SRLOW:1]
  • LATCH_OR_FF=[FF:1]
  • SYNC_ATTR=[ASYNC:1]
SLICEM_G
  • DI=[DI:1] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:1]
  • LUT_OR_MEM=[RAM:1]
SLICEM_WSGEN
  • CK=[CK:1] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:1]
  • WE=[WE_INV:0] [WE:1]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=6
  • PAD=6
IBUF_INBUF
  • IN=6
  • OUT=6
IBUF_PAD
  • PAD=6
IOB
  • O1=15
  • PAD=15
IOB_OUTBUF
  • IN=15
  • OUT=15
IOB_PAD
  • PAD=15
SLICEL
  • BX=15
  • BY=2
  • CE=17
  • CLK=44
  • F1=84
  • F2=83
  • F3=79
  • F4=65
  • G1=89
  • G2=89
  • G3=78
  • G4=58
  • SR=43
  • X=50
  • XQ=36
  • Y=62
  • YQ=16
SLICEL_F
  • A1=84
  • A2=83
  • A3=79
  • A4=65
  • D=85
SLICEL_F5MUX
  • F=14
  • G=14
  • OUT=14
  • S0=14
SLICEL_FFX
  • CE=13
  • CK=36
  • D=36
  • Q=36
  • SR=35
SLICEL_FFY
  • CE=7
  • CK=16
  • D=16
  • Q=16
  • SR=15
SLICEL_G
  • A1=89
  • A2=89
  • A3=78
  • A4=58
  • D=90
SLICEM
  • BY=1
  • CLK=1
  • G1=1
  • G2=1
  • G3=1
  • G4=1
  • SR=1
  • YQ=1
SLICEM_FFY
  • CK=1
  • D=1
  • Q=1
SLICEM_G
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • D=1
  • DI=1
  • WS=1
SLICEM_WSGEN
  • CK=1
  • WE=1
  • WSG=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s500e-fg320-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s500e-fg320-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • netgen -intstyle ise -ar Structure -tm <design> -w -dir netgen/synthesis -ofmt vhdl -sim <fname>.ngc <fname>.vhd
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • netgen -intstyle ise -s 5 -pcf <fname>.pcf -rpw 100 -tpw 0 -ar Structure -tm <design> -w -dir netgen/map -ofmt vhdl -sim <fname>.ncd <fname>.vhd
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 2 2 0 0 0 0 0
map 13 13 0 0 0 0 0
netgen 2 2 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 12 12 0 0 0 0 0
par 12 12 0 0 0 0 0
trce 13 13 0 0 0 0 0
xst 13 13 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_ProjectDescription=Example of prototyping the Timer_MMSS into a NEXYS 2 board from Digilent
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2017-12-08T16:43:30 PROP_intWbtProjectID=E39004A700694042BFAE36691096E094
PROP_intWbtProjectIteration=3 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_lockPinsUcfFile=changed
PROP_AutoTop=true PROP_DevFamily=Spartan3E
PROP_DevDevice=xc3s500e PROP_DevFamilyPMName=spartan3e
PROP_DevPackage=fg320 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-5 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=21
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=3 NGDBUILD_NUM_FDC=23 NGDBUILD_NUM_FDCE=27
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_INV=2 NGDBUILD_NUM_LUT2=15
NGDBUILD_NUM_LUT3=31 NGDBUILD_NUM_LUT3_D=2 NGDBUILD_NUM_LUT3_L=1 NGDBUILD_NUM_LUT4=109
NGDBUILD_NUM_LUT4_D=9 NGDBUILD_NUM_LUT4_L=5 NGDBUILD_NUM_MUXF5=14 NGDBUILD_NUM_OBUF=15
NGDBUILD_NUM_SRL16=1 NGDBUILD_NUM_VCC=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=3 NGDBUILD_NUM_FDC=23 NGDBUILD_NUM_FDCE=27
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=5 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2
NGDBUILD_NUM_LUT2=15 NGDBUILD_NUM_LUT3=31 NGDBUILD_NUM_LUT3_D=2 NGDBUILD_NUM_LUT3_L=1
NGDBUILD_NUM_LUT4=109 NGDBUILD_NUM_LUT4_D=9 NGDBUILD_NUM_LUT4_L=5 NGDBUILD_NUM_MUXF5=14
NGDBUILD_NUM_OBUF=15 NGDBUILD_NUM_SRLC16E=1 NGDBUILD_NUM_VCC=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s500e-5-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5