Timer_MMSS_NEXYS2 Project Status (05/16/2018 - 19:40:38)
Project File: Timer_MMSS_NEXYS2_prj.xise Parser Errors: No Errors
Module Name: Timer_MMSS_NEXYS2 Implementation State: Synthesized
Target Device: xc3s500e-5fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
44 Warnings (42 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 91 4656 1%
Number of Slice Flip Flops 53 9312 0%
Number of 4 input LUTs 175 9312 1%
Number of bonded IOBs 21 232 9%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentmi. 16. may. 19:40:31 2018044 Warnings (42 new)2 Infos (0 new)
Translation ReportOut of Datevi. 8. dic. 17:14:32 2017000
Map ReportOut of Datevi. 8. dic. 17:14:41 201702 Warnings (0 new)2 Infos (0 new)
Place and Route ReportOut of Datevi. 8. dic. 17:15:23 201702 Warnings (1 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportOut of Datevi. 8. dic. 17:15:28 2017   
Bitgen ReportOut of Datevi. 8. dic. 17:17:27 201701 Warning (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
Post-Synthesis Simulation Model ReportOut of Datevi. 8. dic. 17:16:11 2017
Post-Map Static Timing ReportOut of Datevi. 8. dic. 17:16:40 2017
Post-Map Simulation Model ReportOut of Datevi. 8. dic. 17:16:50 2017
WebTalk ReportOut of Datevi. 8. dic. 17:17:28 2017
WebTalk Log FileOut of Datevi. 8. dic. 17:17:33 2017

Date Generated: 05/16/2018 - 19:40:41